Integrated circuits can be designed using high-level description languages such as VHDL (Very High Speed Integrated Circuit Hardware Description Language).
By means of this design technique and the use of appropriate silicon compilers, it is possible to obtain an integrated component having the characteristics specified using the high-level language, for example, the VDHL description.
It is known that the VHDL descriptions of predetermined functions such as those relating to a decoding circuit can constitute libraries of modules referred to as IP or Intellectual Property libraries whereby highly complex electronic devices such as SOC (System On Chip) systems can be constructed.
A distinguishing feature of the modules belonging to an IP library (IP modules or modules) is that they can be used in the design of multiple electronic devices, thanks to the fact that their interface parameters with other modules or electronic circuits can be “specialized” before silicon compilation, assigning specific values to variables or parameters determined at the design stage.
In accordance with the object of the present invention, reference is made to the IP module for telecommunications and the corresponding decoding circuits that can be used in devices for decoding concatenated convolutional codes (turbo decoding).
With reference to the transmission of digital information (data), it is known that the errors introduced when transmitting data on a channel make it necessary to code said data by adding redundancy bits prior to transmission, and to decode them after they are received by removing the redundancy bits. Essentially, thanks to the presence of the redundancy bits, encoding and decoding make it possible to reconstruct the initial data with a level of certainty or probability which allows for the errors introduced by the transmission channel involved.
A variety of well-known techniques can be used to encode and decode data.
For the purposes of the present invention, the convolutional encoding and decoding technique is taken into consideration, and the concatenated type, turbo encoding and decoding, in particular.
As is known, a convolutional encoding device is capable of using predetermined algorithms to take the information which precedes encoding, i.e., a priori information, into account when encoding data. As is also known, the extent to which encoding is reliable, or in other words the extent to which it guarantees that data will be correctly reconstructed, is directly proportional to the amount of a priori information that the encoding algorithm takes into account. Naturally, the complexity of the algorithm used in encoding and decoding will increase along with the amount of a priori information it considers.
To improve the results that can be attained with decoding and to reduce the complexity of the encoding and decoding circuits and devices required for any given level of performance, the so-called turbo encoding and decoding devices have been introduced.
Whether used for encoding or decoding, turbo devices comprise a plurality of convolutional circuits interconnected in concatenated fashion by means of one or more circuits (known as interleaver circuits) capable of delaying or changing the order of the bits.
In general, the architecture of turbo encoding devices (turbo encoders) thus involves using a plurality of convolutional encoding circuits interconnected using serial or parallel layouts in such a way that encoding is performed in parallel or serially.
For example, a convolutional encoding circuit (encoding circuit) 10 (FIG. 1) for turbo encoders includes a data input (u) and two outputs, one for input data (u), in which case the circuit is referred to as systematic, and one for encoding information (code) (c).
In addition, the circuit includes a shift register 12 having a length in number of bits (ν−1) which in the example is three bits, i.e., bit 21, bit 22 and bit 23 respectively. This shift register is capable of receiving data (u) at input and of outputting the code (c) in accordance with the type of internal connections used in encoding circuit 10.
The main parameters that characterize encoding circuit 10 are as follows:    k denotes the number of bits introduced in sequence per unit of time. In the example and in general, encoding with k=1 is used.    k*(ν−1) denotes the size of the shift register 12 to be used for encoding.    n denotes the number of bits output by the encoder.
In general, an encoder receives k bits at a time, which are introduced in the shift register 12 featuring k*(ν−1) positions; at the encoder output, there will be n output bits for every k input bits (n≧k). Each output bit is calculated via a binary or modulo-2 sum of a certain number of bits in shift register 12; naturally, this sum depends on the encoder's internal connection logic and establishes the so-called generator polynomials, which will be discussed in detail later. In the example, the value u of the input bit is added to the value of a bit obtained via a feedback connection (path). The value thus obtained is then added to the value of the first bit 21 of shift register 12 and the result is added to the value of the third bit 23 of shift register 12; in the feedback path, moreover, the third bit 23 and the second bit 22 of shift register 12 are added to the input bit.
As known, encoding circuits 10 are referred to as recursive in cases where feedback connections are present.
In this way, each coded bit (c) depends not only on the k bits received at any given instant, but also on the k* bits (ν−1) received previously.
In accordance with the prior art, the term “codeword” is used to designate the set of n bits supplied at the encoder output. In the example there are two codewords, viz., the data provided at input (u) and the associated code (c). The value k/n is called the “code rate”.
In general, encoding circuits' performance characteristics are defined on the basis of the parameters indicated above. In particular, these characteristics include:                ν Constraint length of the decoding circuit or code, which naturally depends on the length of the shift register,        Nst Number of states corresponding to the value 2k(ν−1) and which corresponds to the number of possible binary combinations in the shift register,        gc Generator polynomial for c, which defines the interconnections for generating code c, and        gf Generator polynomial for fm which defines the interconnections for generating feedback information f.        
As is known, the generator polynomial is uniquely identified by a binary word consisting of ν bits. Each bit of the binary word corresponds to a position of the input data or of the shift register and, by convention, if the bit is at value 1 in the generator polynomial, the input data or that stored in the shift register in the corresponding position participates in computing the feedback or output code. If the bit is at value 0, it does not participate.
In the example shown in FIG. 1, ν is equal to 4 bits, the polynomial gc is, as will be readily apparent to specialists in the field, 1101 (13 DEC), while polynomial gf is 1011 (11 DEC).
Encoding is generally described with a so-called trellis diagram.
For the encoding circuit in FIG. 1, for example, FIG. 2 shows the corresponding trellis diagram 20 where all possible changes in the encoding circuit over time for the various input values u and circuit state are expressed graphically using connecting lines called edges. Trellis diagram 20 also shows output data. i.e., u and c respectively, on the edges.
The foregoing considerations regarding the performance characteristics of encoding circuits for turbo devices also apply to the characteristics of decoding circuits for turbo devices (turbo decoders) given that, as will be readily apparent to a specialist in the field, decoding circuits must have characteristics which are equivalent to those of encoding circuits if they are to be able to decode coded information correctly.
Naturally, input information for decoding circuits consists of bits for systematic information estimation (u) and of bits for redundancy information estimation (c) obtained in accordance with the prior art at the output of the transmission channel following a demodulation operation.
The type of encoding used by the turbo device, e.g., parallel or serial, is another of the parameters to be considered in implementing both turbo decoders and the decoding circuits they contain.
A technical disadvantage of prior art systems for designing turbo decoders is that there are no available IP modules of decoding circuits which can be used regardless of variations in characteristics.
In particular, known IP modules for generating convolutional code decoding circuits are constrained to performance characteristics, and there is thus a one-to-one correspondence between IP modules and the decoding circuits having a given set of performance characteristics.
A further disadvantage of prior art systems is that there are no available IP modules of decoding circuits that can be used regardless of variations in encoding mode.
Naturally, thus means that the IP modules of decoding circuits that can be used in turbo decoders differ according to the turbo encoding mode involved.
In addition, known IP modules of decoding circuits are constrained to the use of specific methods and technologies.
Essentially, known IP modules of decoding circuits are not parametric as regards the performance characteristics of the architecture and the decoder and, because of this limitation, make it necessary to make design choices very early in the process. If, conversely, these modules were parametric and flexible, these choices could be made at later stages. This would provide clear advantages, particularly in cases where it becomes necessary to change the characteristics of the algorithms to be used or the architecture.
Yet another technical disadvantage which specifically affects decoder circuits implemented on silicon or using programmable logic is that once implemented, these circuits can use only one generator polynomial, or in other words only one type of decoding function for reconstructing initial data.
This is an extremely significant limitation of prior art systems, particularly in the case of turbo devices which use serial decoding.
In serial mode decoding, as is known, a second decoding circuit or stage is occupied in decoding at different times than the first circuit or stage, given that information from the first stage must be used for decoding. It is thus possible in principle to use a single decoding circuit in turbo decoders which employ serial decoding approaches.
With prior art systems, however, using a single decoding circuit is possible only if the turbo decoder's decoding stages use a single pair of generator polynomials.
In cases where two or more decoding stages use different generator polynomials, this constraint means that serial turbo decoders must include a corresponding number of decoding circuits, which clearly increases the device's complexity and the associated development costs, given that each individual decoding circuit generally contains a large number of equivalent gates, e.g., around 150,000.
Naturally, this constraint would be overcome if decoder circuits for turbo devices existed which could manage a plurality of generator polynomials.